Vivado+Verilog学习笔记（一）

    `timescale 1ns / 1ps
    module led_test(
    input clk,
    input rst,
    (* MARK_DEBUG="true" *)output reg[3:0] led
    );
    (* MARK_DEBUG="true" *)reg[31:0] counter;
    always@(posedge clk or negedge rst)
    begin
        if(!rst)
            begin
                led <= 4'd0;
                counter <=0;
                
            end
        else if(counter > 32'd 24_999_999)
            begin
               
                counter <=32'd0;
                 led <= ~led;
            end
         else
            begin
                led <=led;