时钟奇偶分频

    // 偶数N分频
    // 计数器位宽 X 
    module div(
    input clk,
    input rst_n,
    output out_clk);
    reg out_clk;
    reg [X:0] cnt;
    
    always @(posedge clk or negedge rst_n)
    if(!rst_n) begin
    cnt <= 0; out_clk <= 0;
    else if(cnt == N/2 - 1) begin
    cnt <= 0; out_clk <= ~out_clk;
    end
    else begin
    cnt <= cnt + 1'b1; out_clk <= out_clk;
    end
    endmodule
     
    
    
      
      
      
      
      
      
      
      
      
      
      
      
      
      
      
      
      
      
      
      
    

    // 奇数N分频
    /