基于2ASK调制解码器的VERILOG实现

    调制模块
    module two_ASK(clk,reset,x,y);
    input clk;
    input reset;
    input x;
    output y;
    reg[1:0]cnt;
    reg carriers;
    
    always@(posedge clk)begin
       if(!reset)begin
       cnt<=2'b00;
          carriers<=0;
       end
       else begin
     if(cnt==2'b11)begin
          cnt<=2'b00;
              carriers<=~carriers;
     end
     else begin
              carriers<=carriers;
              cnt<=cnt+1;
          end
     end
    end
    
    assign y=x&carriers;
    
    endmodule
    
    
    解调模块
    module Ask_two(clk,reset,x,y);
       input clk;
       inp