模N counter with enable signal

    // 模N，计数器位宽X
    module count(
    input clk,
    input rst_n,
    output cnt,
    output en);
    reg [X:0]cnt;
    reg en;
    
    always @(posedge clk or negedge rst_n)
    if(!rst_n) begin
    cnt <= X'b0;
    en <= 0; end
    else if(cnt == X'd(N-1)) begin
    cnt <= X'd0;
    en <= 1'b1; end
    else begin
    cnt <= cnt + 1'b1;
    en <= 1'b0; end
    endmodule