数字IC设计笔试面试题（二）

 //上升沿检测

    
 `timescale 1ns/1ps
    
 module  edge_detect(
    
 	//system signals
    
 	input				clk				, 
    
 	input				rst_n			,
    
 	input 				edge_signal     ,
    
 	output				pulse
    
 );
    
 reg edge_reg0;
    
 reg edge_reg1;
    
 always @(posedge clk or negedge rst_n) begin
    
 	if (!rst_n) begin
    
 		edge_reg0 <= 1'b0;
    
 		edge_reg1 <= 1'b0;
    
 	end
    
 	else begin
    
 		edge_reg0 <= edge_signal;
    
 		edge_reg1 <= edge_reg0;
    
 	end
    
 end
    
 assign pulse = ((~edge_reg1)&edge_reg0)?1'b1:1'b0;
    
 endmodule