＜数字小IP设计＞ （3）：事件驱动机制下的数据流生成模块

    module INTERRUPT(
    input clk_i,
    input rst_i,
    input en_i,
    input clr_i,
    input type_i,
    input pn_i,
    input select_i,
    input dat_i,
    output reg intr_flg_o
    );
    reg dat_d;
    wire dat_pos,dat_neg,dat_pn;
    always @ (posedge clk_i or posedge rst_i)
    begin
    if(rst_i)
    dat_d <= 1'b0;
    else
    dat_d <= dat_i;
    end
    assign dat_pos = dat_i & ~ dat_d;
    assign dat_neg = ~ dat_i & dat_d;
    assign dat_pn  = dat_pos|dat_neg;
    
    parameter rise = 00, fall = 01, high = 10, low = 11;
    
    always @ (psoedge clk_i or posedge rst_i)