逻辑移位与算术移位

    module shift(a,b);
    
    input			[2:0]	a;
    input	signed	[2:0]	b;
    wire 			[3:0] left1_l,left1_a;
    wire	signed	[3:0] left2_l,left2_a;
    wire	[2:0]	right1_l,right1_a;
    wire	signed	[2:0]	right2_l,right2_a;
    
    //无符号数左移
    assign left1_l = a<<1;
    assign left1_a = a<<<1;
    
    //有符号数左移
    assign left2_l = b<<1;
    assign left2_a = b<<<1;
    
    //无符号数右移
    assign right1_l = a>>1;
    assign right1_a = a>>>1;
    
    //有符号数右移
    assign right2_l = b>>1;
    assign right2_a = b>>>1;
    endmodule
    
    
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