Mentor-dft 学习笔记 day32测试模式验证

Macro Test Examples

Example 1 — Basic 1-Cycle Patterns

Verilog Contents:

RAM mem1 (.Dout ({ Dout[7],Dout[6],Dout[5],Dout[4],Dout[3],

Dout[2], Dout[1], Dout[0]}),

.RdAddr ({ RdAddr[1], RdAddr[0] }),

.RdEn ( RdEn ),

.Din ({ Din[7], Din[6], Din[5], Din[4], Din[3],

Din[2], Din[1], Din[0]}) ,

.WrAddr ({ WrAddr[1], WrAddr[0] }), .WrEn ( WrEn ));

ATPG Library Contents:

model RAM (Dout, RdAddr, RdEn, Din, WrAddr, WrEn) (

input (RdAddr,WrAddr) (array = 1 : 0;)

input (RdEn,WrEn) ()

input (Din) (array = 7 : 0;)

output (Dout) (

array = 7 : 0;

data