序列检测-移位寄存器+FSM

    module seqchk(
    input x,
    input clk,
    input rst_n,
    output z,
    output [4:0]q);
    reg [4:0]q;
    reg [4:0]q_dly;
    //将串行数据转为并行，再检测与目标数据是否一致
    always @(posedge clk or negedge rst_n)
    if(!rst_n) q <= 5'b0;
    else q_dly <= q;
    // 将q的数据延迟一个clk，使得z和x对齐
    assign q_dly = {q[3:0],x}
    assign z = {q_dly == 5'b10010}:1:0;
    endmodule