FPGA部分重配置的概述（基于硬件设计）

1.1 Overview

Timemultiplex hardware dynamically on a single FPGA is advantageous:

figure1.1 Basic Premise of Partial Reconfiguration

Once a complete BIT file has configured the FPGA, partially available portions of it can be downloaded to alter regions that are programmable in the FPGA without jeopardizing the functional integrity of applications running on parts of the device that remain unprogrammed.

Partial Reconfiguration is time multiplex ,and it's advantage :

Reducing the FPGA size needed to implement a specific function, which leads to

reductionsin cost and power c